Integrated circuits (ICs) are normally made through multiple process steps in a semiconductor wafer fabrication facility, where each process step places a patterned layer on a wafer. In order for the ICs to operate correctly, these patterned layers must be aligned accurately with each other. Misalignment between the patterned layers may cause short circuits or connection failures which significantly impact device yield. Misalignment measurement between patterned layers, i.e. overlay (OVL) metrology, on the wafer is one of the most important processes in the manufacturing integrated circuit devices. In particular, OVL metrology refers to the determination of the alignment accuracy of one patterned layer with respect to another patterned layer next to it. With the increase in complexity of integrated circuits, the measurement of the OVL metrology becomes more and more important and difficult.
In a traditional fabrication facility that manufactures different product wafers with different patterns and feature sizes, integrated metrology (IM) systems have a fixed setting for performing OVL measurements, irrespective of the different product wafers that pass through them. Different product wafers are produced with different patterns and by different processes. The different processes (or variations within a single process) generate wafers having different surface topographies, which effect OVL measurements and error rates. Current systems utilize alignment markings on a front side of the wafer to provide OVL alignment prior to exposing the wafer to a radiation source. Notably, the current system utilizes alignment markings that are only able to compensate for linear OVL errors and cannot compensate for non-linear OVL errors, such as errors formed in a Z-axis.